The present invention relates generally to a delay locked loop (DLL) circuit and a DLL control method and more particularly to DLL circuit and DLL control method for locking and outputting rising and falling phases of a clock signal.
In a semiconductor device, such as a semiconductor memory, an external clock signal is typically used to synchronize data transfer. In such a semiconductor memory, data can be input and output on rising and falling edges of the external clock signal. A delay locked loop (DLL) circuit can be incorporated in such a device in order to generate an internal clock signal that is synchronized with the external clock signal. A DLL circuit uses a variable delay to delay an internal clock signal so that the edges become synchronized (phase matching) with the external clock signal. Thus, an accurate DLL circuit requires a circuit for accurately generating a phase delay.
Referring now to FIG. 1, a block schematic diagram of a conventional DLL circuit is set forth and given the general reference character 100.
Conventional DLL circuit 100 synchronizes an output clock signal with both the rising and falling edges of an external clock signal.
Conventional DLL circuit 100 includes a first DLL system 101 and a second DLL system 102. First DLL system 101 receives an external clock signal D101 and a reference clock D102 and generates a first internal clock signal D104. Second DLL system 102 receives external clock signal D101 and reference clock D102 and generates a second internal clock signal D106.
First DLL system 101 includes a first phase detection circuit 111, a first arbitrary phase generation circuit 112, and a buffer 113. First phase detection circuit 111 receives the external clock signal D101 and first internal clock signal D104 as inputs and generates a phase detection result signal D103. First arbitrary phase generator circuit 112 receives reference clock D102 and phase decision result signal D103. First arbitrary phase generator circuit 112 delays the phase of reference clock signal D102 based upon the value of phase decision result signal D103 to generate delayed clock signal D102xe2x80x2. Buffer 113 receives delayed clock signal D102xe2x80x2 and generates first internal clock signal D104.
First internal clock signal D104 is input into first phase decision circuit 111. First phase decision circuit compares the rising edge of external clock signal D101 with first internal clock signal D104 and outputs first phase decision result signal D103. First phase decision result signal D103 indicates the phase difference between the rising edges of external clock signal D101 and first internal clock signal D104. When external clock signal D101 and first internal clock signal D104 having rising edges that are coincident with each other in their phases, delayed clock signal 102xe2x80x2 becomes locked in its phase.
Second DLL system 102 includes a second phase detection circuit 114, a second arbitrary phase generation circuit 115, and a buffer 116. Second phase detection circuit 114 receives the external clock signal D101 and second internal clock signal D106 as inputs and generates a phase detection result signal D105. Second arbitrary phase generator circuit 115 receives reference clock D102 and phase decision result signal D105. Second arbitrary phase generator circuit 115 delays the phase of reference clock signal D102 based upon the value of phase decision result signal D105 to generate delayed clock signal D102xe2x80x3. Buffer 116 receives delayed clock signal D102xe2x80x3 and generates second internal clock signal D106.
Second internal clock signal D106 is input into second phase decision circuit 114. Second phase decision circuit compares the falling edge of external clock signal D101 with second internal clock signal D106 and outputs second phase decision result signal D105. Second phase decision result signal D105 indicates the phase difference between the falling edges of external clock signal D101 and second internal clock signal D106. When external clock signal D101 and second internal clock signal D106 having falling edges that are coincident with each other in their phases, delayed clock signal 102xe2x80x3 becomes locked in its phase.
Referring now to FIGS. 2(a)-(c), a timing diagram illustrating external clock signal D101, first internal clock signal D104, and second internal clock signal D106 is set forth.
The timing diagram of FIGS. 2(a)-(c) illustrates signals generated by conventional DLL circuit 100 when the high edged pulse width of first and second internal clock signals (D104 and D106) is greater than the high pulse width of external clock signal D101. It is noted that only one edge of first internal clock signal D104 (rising edge) and second internal clock signal D106 (falling edge) has a phase that is locked with external clock signal D101. Thus, the pulse widths of the first and second internal clock signals (D104 and D106) is not set by the phase of external clock signal D101. So, even though the first and second internal clock signals (D104 and D106) have the same period (T1) as the external clock signal D101, the waveforms do not match.
Referring now to FIGS. 3(a)-(c), a timing diagram illustrating external clock signal D101, first internal clock signal D104, and second internal clock signal D106 is set forth.
The timing diagram of FIGS. 3(a)-(c) illustrates signals generated by conventional DLL circuit 100 when the high edged pulse width of first and second internal clock signals (D104 and D106) is less than the high pulse width of external clock signal D101. It is noted that only one edge of first internal clock signal D104 (rising edge) and second internal clock signal D106 (falling edge) has a phase that is locked with external clock signal D101. Thus, the pulse widths of the first and second internal clock signals (D104 and D106) is not set by the phase of external clock signal D101. So, even though the first and second internal clock signals (D104 and D106) have the same period (T1) as the external clock signal D101, the waveforms do not match.
In conventional DLL circuit 100 first DLL system 101 and second DLL system 102 each have an arbitrary phase generator circuit (112 and 115) in order to create internal clock signals (D104 and D106) that are locked, respectively, with a rising edge and falling edge of external clock signal D101. Arbitrary phase generator circuits (112 and 115) require a large amount of chip area compared to the other circuits in the conventional DLL circuit 100. In order to generate a clock with reduced jitter having an arbitrary phase using arbitrary phase generator circuit (112 and 115), a large amount of chip area may be required, which increases manufacturing costs. Also, power consumption of arbitrary phase generator circuits (112 and 115) is a large portion of the power consumed in the conventional DLL circuit 100.
Also, because a separate internal clock signal (D104 and D106) are generated in order to have internal clocks that are locked in phase with the rising and falling edges, respectively, of external clock signal D101, a circuit that is clocked off one edge may receive a different signal than one clocked off the opposite edge. This can increase signal routing and consume chip area.
In view of the above discussion, it would be desirable to provide a DLL circuit that may be capable of outputting a single system clock signal in synchronism with both rising and falling edges of an external clock signal. It would also be desirable to provide a DLL control method for controlling the DLL circuit. It would be desirable to provide a DLL circuit having reduced power consumption compared to conventional approaches. It would also be desirable to provide a DLL circuit, which occupies a reduced chip area as compared to conventional approaches.
According to the present embodiments, a delay locked loop (DLL) circuit having an internal clock signal with positive and negative clock edges locked with an externally applied clock signal is provided. The DLL circuit may include a first phase decision circuit, a second phase decision circuit, an arbitrary phase generator circuit, and a variable pulse width circuit. The first phase decision circuit may receive an the external clock signal and internal clock signal and may generate a phase decision signal that may indicate whether a first edge of the internal clock signal is to be sped-up or delayed. The arbitrary phase generator may provide a phase shifted signal based on the phase decision signal. The second phase decision circuit may receive the external clock signal and the internal clock signal and may generate a phase decision signal that may indicate whether a second edge of the internal clock signal is to be sped-up or delayed. The variable pulse width circuit may receive the phase shifted signal and delay a second edge based on the phase decision signal.
According to one aspect of the embodiments, an external clock may have a first external clock edge and a second external clock edge. An internal clock may have a first internal clock edge and a second internal clock edge. A first phase decision circuit may receive the external clock and the internal clock and may provide a first phase decision signal based on a phase relationship between the first external clock edge and the first internal clock edge. An arbitrary phase generator circuit may receive the first phase decision signal and may provide an adjusted phase clock having a phase based on the value of the first phase decision signal. A variable pulse width circuit may receive a second phase decision signal and may delay the second internal clock edge based on the value of the second phase decision signal.
According to another aspect of the embodiments, the first internal clock edge may be substantially locked with the first external clock edge. The second internal clock edge may be substantially locked with the second external clock edge.
According to another aspect of the embodiments, the first internal clock edge and the first external clock edge may be positive transitioning edges. The second internal clock edge and the second external clock edge may be negative transitioning edges.
According to another aspect of the embodiments, the first internal clock edge and the first external clock edge may be negative transitioning edges. The second internal clock edge and the second external clock edge may be positive transitioning edges.
According to another aspect of the embodiments, the arbitrary phase generator may receive a reference clock and may provide the adjusted phase clock being phase shifted from the reference clock.
According to another aspect of the embodiments, the arbitrary phase generator may include a phase clock signal generator, a phase control circuit, and a clock signal select circuit. The phase clock signal generator may receive the reference clock and may provide a plurality of phase shifted clock signals. The phase control circuit may receive the first phase decision signal and may provide at least one clock select signal. The clock signal select circuit may receive the at least one clock select signal and select one of the plurality of phase shifted clock signals to generate the adjusted phase clock.
According to another aspect of the embodiments, the DLL circuit can include a reference clock having a first reference clock edge and a second reference clock edge, a locked clock having a first locked clock edge and a second locked clock edge, a first delay circuit providing a delay in a subsequent first locked clock edge based on the timing of a previous first locked clock edge, and a second delay circuit providing a delay in a subsequent second clock edge based on the timing of a previous second locked clock edge.
According to another aspect of the embodiments, the second delay circuit may receive a phase decision result signal having a logic value based on the timing of the second reference clock edge with respect to the second latched clock edge. The second delay circuit may include a delay control circuit and a delay generator. The delay control circuit may receive the phase decision result signal and may provide a first delay potential. The delay generator may receive the first delay potential provide the locked clock signal in which the second locked clock edge is delayed according to the first delay potential.
According to another aspect of the embodiments, the second delay circuit may include a first controllable impedance device that may receive the first delay potential and provide an impedance based on the first delay potential. The second locked clock edge may be delayed according to the impedance of the first controllable impedance device.
According to another aspect of the embodiments, the second delay circuit may include a second delay potential provided by the second delay control circuit. A second controllable impedance path may receive the second delay potential and may provide an impedance based on the second delay potential. The second locked clock edge may be delayed according to the impedance of the first controllable impedance device and the impedance of the second controllable impedance device.
According to another aspect of the embodiments, a first impedance control node may receive the first delay potential. The delay control circuit may include a first capacitor connected to the first impedance control node. A second impedance control node may receive the second delay potential. The delay control circuit may include a second capacitor connected to the second impedance control node.
According to another aspect of the embodiments, the first locked clock edge and first reference clock edge may be positive clock edges. The second locked clock edge and second reference clock edge may be negative clock edges.
According to another aspect of the embodiments, the first locked clock edge and first reference clock edge may be negative clock edges. The second locked clock edge and second reference clock edge may be positive clock edges.
According to another aspect of the embodiments, a first phase decision circuit may receive the reference clock and the locked clock and may generate a first phase decision result signal based on the timing of the first reference clock edge and the first locked clock edge. The first delay circuit may receive the first phase decision result signal. The first phase decision circuit may include a latch circuit that may receive the reference clock and a reference potential and may latch a first decision logic level if the reference clock has a potential greater than the reference potential at the first locked clock edge. The first latch circuit may latch a second decision logic level if the reference clock has a potential lower than the reference potential at the first locked clock edge.
According to another aspect of the embodiments, a second phase decision circuit may receive the reference clock and the locked clock and may generate a second phase decision result signal based on the timing of the second reference clock edge and the second locked clock edge. The second delay circuit may receive the second phase decision result signal. The second phase decision circuit may include a second latch circuit that may receive the reference clock and a reference potential and may latch a third decision logic level if the reference clock has a potential greater than the reference potential at the second locked clock edge. The first latch circuit may latch a fourth decision logic level if the reference clock has a potential lower than the reference potential at the second locked clock edge.
According to another aspect of the embodiments, a delay locked loop (DLL) control method may include comparing a first phase of an external clock with a first phase of an internal clock and generating a first comparison result, generating an adjusted clock from a reference clock based on the first comparison result, and adjusting the pulse width of the adjusted clock to generate the internal clock.
According to another aspect of the embodiments, adjusting the pulse width of the adjusted clock may include comparing a second phase of the external clock with a second phase of the internal clock and generating a second comparison result, and adjusting the pulse width of the adjusted clock based on the second comparison result.
According to another aspect of the embodiments, comparing the second phase of the external clock with the second phase of the internal clock may include enabling a second phase decision circuit based on a second internal clock edge to generate the second comparison result based on the logic level of the external clock.
According to another aspect of the embodiments, adjusting the pulse width of the adjusted clock may include modifying the propagation delay of a delay circuit by adjusting the impedance of a controllable impedance path.
According to another aspect of the embodiments, generating an adjusted clock from a reference clock may include generating complementary clock signals that may be phase shifted from the reference clock according to the first comparison result.